Memory defect redress analysis treating method, and memory testing apparatus performing the method

ABSTRACT

There are provided a failure repair analyzing and processing method and a memory testing apparatus provided with a failure repair analyzing and processing apparatus using this method, that are capable of reducing a time duration required to perform the failure repair analysis and processing for a multi-bit memory having redundancy structure. A plurality of repair analysis units as well as a common failure analysis memory are provided, and these repair analysis units are concurrently operated in parallel with each other, thereby to carry out respective repair analyses and processings for failure memory cells of plural data bits read out from the failure analysis memory in the plural repair analysis units concurrently and in parallel with each other. As a result, a time duration required to execute the failure repair analysis and processing is shortened.

TECHNICAL FIELD

[0001] The present invention relates to a method of analyzing andprocessing a repair of failure in a memory, that comprises the step ofanalyzing as to whether a failure memory cell or cells existing in amemory having redundancy structure tested by a memory testing apparatuscan be repaired or relieved or not, and a memory testing apparatus usingthe method.

BACKGROUND ART

[0002] Memory testing apparatuses for testing various types ofsemiconductor memories including, for example, a memory (IC memory)constructed by a semiconductor integrated circuit (IC) can beclassified, roughly, into a memory testing apparatus for testing amemory in wafer state before packaged and a memory testing apparatus fortesting a memory after packaged. The memory testing apparatus fortesting a memory in wafer state before packaged differs remarkably fromthe memory testing apparatus for testing a memory after packaged in thatthe former apparatus is provided with a failure repair processingfunction or means that decides whether a failure memory cell or cellsexisting in a memory having redundancy structure described later on canbe repaired or not.

[0003] In recent years, a semiconductor memory (particularly, an ICmemory) has a tendency that its storage capacity is increased and thatits size is miniaturized, and with the increased memory capacity and theminiaturization, a defect rate of IC memories has been increased. Inorder to lower the defect rate of IC memories, in other words, in orderto prevent the yield of IC memories from being decreased, there has beenmanufactured, for example, an IC memory in which a failure memory cellor cells detected therein can be electrically replaced with a sparememory cell or cells (called a spare line, a repair line or a redundancycircuit in this technical field). An IC memory of this type that has aspare memory cell or cells (hereinafter, referred to as spare line)formed therein is called a memory having redundancy structure in thistechnical field, and analysis as to whether a repair of a failure memorycell or cells existing in this memory of redundancy structure can beeffected or not is carried out in a failure repair analyzing andprocessing apparatus.

[0004] A prior memory testing apparatus provided with a failure repairanalyzing and processing apparatus of this type is shown in FIG. 4 in ablock diagram by a rough construction thereof. This memory testingapparatus TES comprises, roughly speaking, a main controller 111, apattern generator 112, a timing generator 113, a waveform formatter 114,a logical comparator 115, a driver 116, an analog level comparator(hereinafter, referred to as comparator) 117, a failure analysis memory118, a failure repair analyzing and processing apparatus 119, a logicalamplitude reference voltage source 121, a comparison reference voltagesource 122, and a device power source 123. Further, in the followingdescription, a case of testing an IC memory in wafer state beforepackaged will be described. However, in cases of testing various kindsof semiconductor memories in wafer state before packaged in addition toIC memories, testing thereof will be carried out in the same manner.

[0005] The main controller 111 is generally constituted of a computersystem and a test program PM created by a user (programmer) ispreviously loaded therein. This main controller 111 controls the wholeof the memory testing apparatus in accordance with the test program PM.The main controller 111 is connected, via a tester bus TBUS, to thepattern generator 112, the timing generator 113, the waveform formatter114, the logical comparator 115, the failure analysis memory 118, thefailure repair analyzing and processing apparatus 119, the logicalamplitude reference voltage source 121, the comparison reference voltagesource 122, the device power source 123, and the like.

[0006] An IC memory to be tested (memory under test) 200 is formed intoa semiconductor wafer WH in this example. Before testing of the memoryunder test 200 is started, various kinds of data are, at first, set fromthe main controller 111. The pattern generator 112 supplies test patterndata to the waveform formatter 114 in accordance with the test programPM. On the other hand, the timing generator 113 generates timing signals(clock pulses) for controlling operation timings of the waveformformatter 114, the logical comparator 115, and the like.

[0007] The waveform formatter 114 converts the test pattern datasupplied from the pattern generator 112 into a test pattern signalhaving a real waveform. This test pattern signal is applied to thememory under test 200 via the driver 116 which in turn amplifies involtage the test pattern signal to a waveform having an amplitude valueset by the logical amplitude reference voltage source 121. The testpattern signal is stored in a memory cell of the memory under test 200,that has an address specified by an address signal, and the storagecontent is read out therefrom in a read cycle later on.

[0008] A response signal read out from the memory under test 200 iscompared with a reference voltage supplied from the comparison referencevoltage source 122 in the comparator 117, and it is determined whetheror not the response signal has a predetermined logical level, i.e.,whether or not the response signal has a voltage of a predeterminedlogical H (logical high) or a voltage of a predetermined logical L(logical low). The response signal determined to have the predeterminedlogical level is sent to the logical comparator 115, where the responsesignal is compared with an expected value signal outputted from thepattern generator 112, and it is decided whether or not the memory undertest 200 has outputted a normal response signal.

[0009] If the response signal does not coincide with the expected valuesignal, the memory cell of the memory under test 200, that has theaddress from which that response signal has been read out is determinedto be in failure, and a failure signal (failure data) indicating thatfact is generated from the logical comparator 115.

[0010] Usually, the failure analysis memory 118 has the same operationspeed and storage capacity as those of the memory under test 200, andthe same address signal as an address signal applied to the memory undertest 200 is applied to the failure analysis memory 118. In addition, thefailure analysis memory 118 is initialized prior to starting thetesting. For example, by the initialization, a data of logical “0” iswritten in all of the addresses of the failure analysis memory 118. Eachtime a failure data representing the disagreement between the responsesignal and the expected value signal is generated from the logicalcomparator 115 during the testing of the memory under test 200, afailure data (for example, logical “1” data) indicating that the testedmemory cell is in failure is written in the same address of the failureanalysis memory 118 as that of the memory cell of the memory under test200 from which the disagreement has occurred.

[0011] On the contrary, when the response signal coincides with theexpected value signal, the memory cell of the memory under test 200having the address from which the response signal has been read out isdetermined to be normal, and a pass signal indicating that fact isgenerated. This pass signal is usually not stored in the failureanalysis memory 118.

[0012] At the time point when the testing has been completed, thefailure data stored in the failure analysis memory 118 are read outtherefrom into the failure repair analyzing and processing apparatus120, and it is decided whether the failure memory cells of the tested ICmemory 200 can be repaired or not. In general, in addition to theaddresses of the failure memory cells of the memory under test 200, thetest patterns given to those failure memory cells are also stored in thefailure analysis memory 118, and at the time point when the testing hasbeen completed, those data are read out from the failure analysis memory118 into the failure repair analyzing and processing apparatus 119 inwhich it is decided whether the failure memory cells can be relieved orrepaired or not.

[0013] Further, in FIG. 4, each of the driver 116 and the comparator 117is illustrated by one symbol. However, in practice, the number ofdrivers 116 provided is equal to the number of input terminals of thememory under test 200, for example, if the number of input terminals is512, then 512 of drivers 116 are provided, and the number of comparators117 provided is equal to the number of output terminals of the memoryunder test 200 (since the number of input terminals provided is usuallyequal to the number of output terminals, the number of comparators 117provided is equal to the number of drivers 116 provided). In addition,though each of the waveform formatter 114, the logical comparator 115,the failure analysis memory 118, the failure repair analyzing andprocessing apparatus 119, etc. is also shown by one block, the remainingelements except for the main controller 111 and the timing generator 112are usually provided as many as the number of the drivers 116 (forexample, 512).

[0014] The storage area of a semiconductor memory is generally dividedinto a plurality of storage regions, and each storage region isconstituted of a large number of memory cells aligned along row addresslines and column address lines, which is called a memory cell array inthis technical field. In addition, each storage region (each memory cellarray) is called a block. The storage capacity of a semiconductor memoryis the sum value of the memory capacities of the plural memory cellarrays.

[0015] In case of a memory having redundancy structure, each of thestorage regions is provided with a desired number of column spare linesand a desired number of row spare lines formed in the row addressdirection and in the column address direction respectively at theperiphery of the memory cell array. Each column spare line includes thesame number of memory cells as that of the column address lines in thememory cell array and each row spare line includes the same number ofmemory cells as that of the row address lines in the memory cell array.

[0016] In addition, in case of a multi-bit memory, a memory elementconstituted of the above-mentioned plural memory cell arrays(hereinafter, referred to as memory cell array group) is formed on thesame semiconductor chip as many as the number of bits. A multi-bitmemory having redundancy structure is shown in FIG. 7.

[0017] A memory 200 shown in FIG. 7 is an (N+1)-bit memory, and a bit-1memory cell array group 201-0 that stores data corresponding to thefirst data bit (bit-0), a bit-2 memory cell array group 201-1 thatstores data corresponding to the second data bit (bit-1), a bit-3 memorycell array group 201-2 that stores data corresponding to the third databit (bit-2), . . . , a bit-N memory cell array group 201-N that storesdata corresponding to the (N+1)th data bit (bit-N) are formed on thesame wafer WH. That is, the same number of the memory cell array groupsas that of bits of a multi-bit test pattern signal to be written in thememory 200 is formed on the same wafer WH. Though these memory cellarray groups are shown in three dimensional manner in FIG. 7, they are,in practice, formed in planar manner.

[0018] A plurality of (six, in this example) memory cell arrays 202 areformed in the inside of each of the plural memory cell array groups201-0, 201-1, 201-2, . . . . In addition, a desired number of columnspare lines SC and a desired number of row spare lines SR are formed inthe row address direction ROW and in the column address direction COLrespectively at the periphery of each memory cell array 202. Further, inthis example, a case is shown that two row spare lines SR are disposedalong one side in the row address direction of each memory cell array202 and two column spare lines SC are disposed along one side in thecolumn address direction of each memory cell array 202. However, it isneedless to say that the number of spare lines and the positions wherethese spare lines are disposed are not limited to the example asillustrated.

[0019]FIG. 5 is a block diagram showing a rough construction of theprior art failure repair analyzing and processing apparatus 119 that isused in testing a multi-bit IC memory such as the multi-bit IC memoryshown in FIG. 7, and FIG. 6 is a block diagram showing a roughconstruction of the prior art failure analysis memory 118 that is usedin testing a multi-bit IC memory.

[0020] As shown in FIG. 6, the failure analysis memory 118 comprises: astorage part AFM provided with a data input terminal Dn, an addressinput terminal An, a data output terminal Qn, etc.; an address selectorfor selecting and taking out an address signal PADR supplied from apattern generator 112; and a multiplexer MUX having one input terminal Ato which an address signal FADR supplied from the failure repairanalyzing and processing apparatus 119 is applied and the other inputterminal B to which an address signal supplied from the address selectorADS is applied, the multiplexer MUX selecting either one of the addresssignal FADR or the address signal PADR to output the selected one.

[0021] As shown in FIG. 5, the failure repair analyzing and processingapparatus 119 comprises: a control part 10 for outputting an analysisstart signal ALSRT, a bit specifying signal BITSP, a load signal LOAD,etc.; and a repair analysis unit 20 that operates under the control ofthe control part 10.

[0022] The repair analysis unit 20 comprises: a bit specifying part 21constituted by a bit specifying register 21A, a group of AND gates 21Band an OR gate 21C for performing a logical addition (OR) of the ANDgate group 21B; a latch circuit 22 for temporarily storing dataoutputted from the bit specifying part 21; an operation and processingpart 23 for performing an operation or computation of data read out fromthe latch circuit 22; a failure block memory 25 for storing a memorycell array from which a failure memory cell is detected; and an addressgenerator 24 for generating an address signal for accessing an addressof the failure analysis memory 118 in carrying out a repair analysis andprocessing. The repair analysis unit 20 starts a repair analyzingoperation when it receives an analysis start signal ALSRT from thecontrol part 10, and sends an analysis end signal ALEND to the controlpart 10 when the repair analyzing operation for one data bit (one memorycell array group) is completed.

[0023] Into the bit specifying register 21A is loaded a bit specifyingsignal BITSP being applied to the data terminal thereof when a loadsignal LOAD is applied thereto from the control part 10, and theregister 21A specifies one data bit (one of the memory cell arraygroups) of the memory under test 200 that a repair analysis andprocessing should be performed. In reality, it specifies the data bitmemory area of the failure analysis memory 118 in which failure dataexisting in one data bit (one memory cell array group) of the memoryunder test 200 have been stored. Each AND gate of the AND gate group 21Bhas two input terminals, and a bit specifying signal BITSP from the bitspecifying register 21A is applied to one input terminal of each ANDgate and a failure data FAIL read out from the data output terminal Qnof the failure analysis memory 118 is sequentially applied to the otherinput terminal of each AND gate. Accordingly, the AND gate group 21B hasthe same number of AND gates provided therein as that of the data bits(the memory cell array groups) of the memory under test 200, and onlyone AND gate corresponding to a bit specifying signal BITSP from the bitspecifying register 21A is enabled.

[0024] During the testing of the memory under test 200, the multiplexerMUX of the failure analysis memory 118 selects the other input terminalB so that the multiplexer MUX supplies address signals PADR to theaddress input terminal An of the storage part AFM, the address signalsPADR being supplied to the other input terminal B from the patterngenerator 112 through the address selector ADS. As a result, each timethe disagreement occurs in the logical comparator 115, a failure dataFAIL applied to the data input terminal Dn of the storage part AFM willbe stored in the same address of the storage part AFM as that of thefailure memory cell of the memory under test 200 from which thatdisagreement has occurred.

[0025] Further, in the specification, “failure data” means data that, incase the memory under test 200 is a multi-bit memory, has the same bitwidth as that of data read out from this memory under test 200 as wellas all bits thereof are logical “0” where no disagreement occur in thelogical comparator 115, and where one or more disagreements occur in thelogical comparator 115, only one or more bits of the data from which theone or more disagreements have occurred are changed to logical “1”. Forexample, in case the memory under test 200 is an eight-bit memory and isconstituted of eight data bits (memory cell array groups), data of eightbits from data bit 1 to data bit 8 is written in the memory under test200. Accordingly, where no disagreement occurs in the logical comparator115, the failure data becomes a data of “00000000” in which all of theeight bits are logical “0”. Where a disagreement is detected in the databit 2, the failure data becomes a data of “01000000”, and where adisagreement is detected in both the data bit 3 and the data bit 6, thefailure data becomes a data of “00100100”. Therefore, if such failuredata are stored in the same addresses of the failure analysis memory 118as the addresses of the memory under test 200 from which those failureshave occurred, the failure occurrence addresses of the memory under test200 and the locations or positions of those failure memory cells can bestored.

[0026] When the testing of the memory under test 200 has been completed,a failure repair analysis and processing of the tested memory 200 iscarried out. The multiplexer MUX of the failure analysis memory 118selects its one input terminal A so that it applies address signals FADRsent to the one input terminal A from the address generator 24 shown inFIG. 5 of the failure repair analyzing and processing apparatus 119 tothe address input terminal An of the storage part AFM, thereby to accessthe failure data stored in the storage part AFM.

[0027] The failure data FAIL read out from the data output terminal Qnof the storage part AFM are supplied, in sequence, to the other inputterminals of the AND gate group 21B of the bit specifying part 21 of thefailure repair analyzing and processing apparatus 119. Since the bitspecifying register 21A controls to enable only one AND gate in the ANDgate group 21B corresponding to one data bit specified by the register,only the failure data (failure data of one bit) existing in the memoryarea of the specified data bit (memory cell array group) among thefailure data FAIL read out from the storage part AFM are taken out intothe latch circuit 22.

[0028] The failure data of one bit taken out into the latch circuit 22are recognized as to in which memory cell array 202 and on which addressline of the recognized memory cell array they exist on the basis ofaddress signals generated from the address generator 24, and further,the location (address) of the failure memory cell on that recognizedaddress line is specified and is sent to the operation and processingpart 23. The operation and processing part 23 adds up in number thefailure data taken therein in each address line for each memory cellarray 202, and operates or computes and processes as to whether theaddress line on which one or more failure memory cells exist can berepaired by use of spare lines SC, SR provided on each memory cell array202.

[0029] Moreover, the operation and processing part 23 reads out thestored data in the failure block memory 25 therefrom, and if there is amemory cell array from which any failure memory cell has not beendetected, the operation and processing part 23 controls such that theaddress generator 24 does not generate an address signal to access thememory cell array from which any failure memory cell has not beendetected and generates an address signal to access a subsequent memorycell array to be analyzed and processed next time from which a failurememory cell or cells have been detected. That is, the repair analysisand processing for each of memory cell arrays from which no failurememory cell has been detected is not carried out and the repair analysisand processing for a subsequent memory cell array to be analyzed andprocessed next time is executed at once.

[0030] In the prior art failure repair analyzing and processing methoddescribed above, failure data in a data bit (memory cell array group)specified by the bit specifying part 21 are read out one bit by one bitusing address signals and are sent to the operation and processing part23. Specifically explaining, in case of a multi-bit memory under test200 shown in FIG. 7, a plurality of memory cell array groups 201-0,201-1, 201-2, . . . , 201-N are specified one memory cell array group byone memory cell array group by the bit specifying part 21, and therepair analysis and processing for (N+1) memory cell array groups 201-0,201-1, 201-2, . . . , 201-N is carried out one group by one group.Accordingly, there is a disadvantage that a time required to execute therepair analysis and processing for (N+1) memory cell array groups comesto considerably long.

[0031] Furthermore, in case of testing a large number of multi-bitmemories each having redundancy structure at the same time, the failureanalysis memory 118 shown in FIG. 6 and the failure repair analyzing andprocessing apparatus 119 shown in FIG. 5 are provided for each memoryunder test. These large number of the failure analysis memories 118 andthe failure repair analyzing and processing apparatuses 119 areconcurrently operated in parallel with one another so that the failurerepair analysis and processing for each of the large number of memoriesunder test is carried out.

[0032] In such case, a failure repair analyzing and processing apparatusthat executes the failure repair analysis and processing for a memoryunder test in which many failure memory cells exist becomes naturallylong in its processing time, and hence the processing speed thereof islowered. As a result, in case the failure repair analysis and processingfor each of the remaining memories under test has been completed, thefailure repair analyzing and processing apparatuses that have completedthe failure repair analysis and processing are stopped to operate, andthe failure repair analysis and processing for a memory under test inwhich many failure memory cells exist is continued in the state that thefailure repair analyzing and processing apparatuses that have completedthe failure repair analysis and processing are waiting on. Accordingly,even there exists only one failure repair analyzing and processingapparatus that takes a long time to carry out the failure repairanalysis and processing for a memory under test, the failure repairanalysis and processing time for the whole apparatuses comes to thefailure repair analysis and processing time for the failure repairanalyzing and processing apparatus that has taken the longest time,which results in a shortcoming that the failure repair analysis andprocessing cannot be carried out at high speed.

[0033] Recently, since the storage capacity of a memory is increasingmore and more and the number of bits of a memory is also increasing,there has been a tendency that the failure repair analysis andprocessing time for a memory having redundancy structure is still moreincreased. For this reason, it is strongly demanded that the failurerepair analysis and processing can be performed at high speed.

DISCLOSURE OF THE INVENTION

[0034] It is an object of the present invention to provide a failurerepair analyzing and processing method by which the failure repairanalysis and processing for a memory having redundancy structure can becarried out at high speed.

[0035] It is another object of the present invention to provide a memorytesting apparatus provided with a failure repair analyzing andprocessing apparatus that is capable of carrying out at high speed thefailure repair analysis and processing for a memory having redundancystructure.

[0036] In order to accomplish the aforesaid objects, in one aspect ofthe present invention, there is provided a method of analyzing andprocessing a repair of failure that is carried out in a memory testingapparatus which comprises: a failure analysis memory for storing thereinfailure data representing a failure memory cell or cells of a memoryunder test having redundancy structure; and a failure repair analyzingand processing apparatus for analyzing as to whether the failure memorycell or cells of the memory under test can be repaired on the basis ofthe failure data read out from the failure analysis memory after thetesting has been completed, the method comprising the steps of: readingout failure data respectively from plural specified data bit memoryareas of the failure analysis memory in sequence and distributing themto corresponding plural repair analysis units respectively; andoperating concurrently the plural repair analysis units in parallel witheach other and causing the units to carry out concurrently their repairanalyses and processings for the failure memory cell or cellscorresponding to the failure data read out from the failure analysismemory in parallel with each other.

[0037] In a preferred embodiment, the aforesaid failure repair analyzingand processing method further includes: the step of checking whetherthere exists an unprocessed data bit memory area for which the repairanalysis and processing is not executed or not, and in case anunprocessed data bit memory area has been detected, each of the repairanalysis units performs, when it has completed the repair analysis andprocessing for failure data of a data bit memory area assigned to thatunit, the repair analysis and processing for failure data of thedetected unprocessed data bit memory area at once.

[0038] In addition, the step of reading out failure data respectivelyfrom plural specified data bit memory areas of the failure analysismemory in sequence includes the step of: switching in sequencerespective address signals accessing to plural specified data bit memoryareas, that are outputted respectively from the plural repair analysisunits to apply them to the failure analysis memory, and the period thatthe plural address signals are switched in sequence is a period that theperiod of each address signal accessing to corresponding one specifieddata bit memory area is divided by the number of specified data bitmemory areas, and the failure data read out from the failure analysismemory are failure data that are switched in sequence at intervals ofthe same period as the switching period of the address signals appliedto the failure analysis memory.

[0039] In another aspect of the present invention, there is provided amemory testing apparatus which comprises: a failure analysis memory forstoring therein failure data representing a failure memory cell or cellsof a memory under test having redundancy structure; a plurality ofrepair analysis units, each being constructed such that it specifies anydata bit memory area in plural data bit memory areas of the failureanalysis memory, reads out failure data stored in the specified data bitmemory area in respective failure data stored in the plural data bitmemory areas of the failure analysis memory, and analyzes as to whethera memory cell array or arrays associated with the read-out failure datacan be repaired or not; access control means for switching in sequencerespective address signals outputted from the plural repair analysisunits to apply them to the failure analysis memory in sequence; datadistributing means for distributing respective failure data read outfrom the plural specified data bit memory areas of the failure analysismemory to the corresponding plural repair analysis units, respectively;and a control part that controls respective repair analysis andprocessing operations of the plural repair analysis units.

[0040] In a preferred embodiment, each of the plural repair analysisunits is provided with its own address generator, and each repairanalysis unit can access the failure analysis memory separately andindependently of the operation of other repair analysis unit or units bygenerating an address signal accessing to a specified data bit memoryarea from its own address generator.

[0041] The access control means is arranged such that it switches insequence respective address signals accessing to plural specified databit memory areas, that are outputted respectively from the plural repairanalysis units to apply them to the failure analysis memory, and theperiod that the plural address signals are switched in sequence is aperiod that the period of each address signal accessing to correspondingone specified data bit memory area is divided by the number of specifieddata bit memory areas, and the failure data read out from the failureanalysis memory are failure data that are switched in sequence atintervals of the same period as the switching period of the addresssignals applied to the failure analysis memory.

[0042] The control part applies respective analysis start signals,respective bit specified signals, and respective load signals to theplural repair analysis units, respectively, and receives a analysis endsignal from each of the plural repair analysis units, thereby to controlrespective repair analysis and processing operations of the pluralrepair analysis units.

[0043] In addition, the control part further comprises: unprocessed databit detecting means for detecting, each time a repair analysis unit thathas completed the repair analysis and processing operation for a memorycell array or arrays associated with failure data of a specified databit memory area transmits an analysis end signal, whether there existsan unprocessed data bit memory area for which the repair analysis andprocessing is not executed or not; and data bit update means forupdating, in case an unprocessed data bit memory area has been detected,a bit specifying signal being applied to a repair analysis unit that hascompleted the repair analysis and processing operation to a bitspecifying signal to be applied to the unprocessed data bit memory area.

[0044] In case the memory under test is a multi-bit memory, the failureanalysis memory includes at least the same number of data bit memoryareas as the number of bits of the memory under test, and failure dataof each of the data bits of the multi-bit memory under test are storedin corresponding one data bit memory area of the failure analysismemory.

[0045] In case the memory under test is a one-bit memory, the failureanalysis memory includes at least the same number of data bit memoryareas as the number of memory cell arrays of the memory under test, andfailure data of each of the memory cell arrays of the memory under testare stored in corresponding one data bit memory area of the failureanalysis memory.

[0046] In accordance with the failure repair analyzing and processingmethod according to the present invention and the memory testingapparatus using this method, since respective repair analyses andprocessings for a plurality of data bits or a plurality of memory cellarrays can be concurrently carried out, if the number of failure repairanalysis units is N, the failure repair analysis and processing can beexecuted at high speed as many as N times.

[0047] Moreover, each of the repair analysis units operatesindependently, and when one repair analysis unit has completed therepair analysis and processing operation for a data bit or memory cellarray assigned thereto, it executes the repair analysis and processingoperation for the next unprocessed data bit or memory cell array.Accordingly, even if there occurs a delay in completion of the repairanalysis and processing operation of one repair analysis unit because itperforms the repair analysis and processing for a memory cell array inwhich many failure memory cells exist and it takes a long time in therepair analysis and processing thereof, the remaining repair analysisunit or units carry out the failure repair analysis and processing foran unprocessed data bit or memory cell array in sequence. As a result,even if a number of failure memory cells exist biasedly in a specifiedmemory cell array, the whole repair analysis and processing time isconsiderably shortened. Thus, it is possible to remove the prior artdisadvantages.

BRIEF DESCRIPTION OF THE DRAWINGS

[0048]FIG. 1 is a block diagram showing a rough construction of anembodiment of the memory testing apparatus according to the presentinvention that is provided with a failure repair analyzing andprocessing apparatus using a method of analyzing and processing a repairof failure in a memory according to the present invention;

[0049]FIG. 2 is a block diagram showing a detailed construction of thefailure repair analyzing and processing apparatus shown in FIG. 1;

[0050]FIG. 3 is a timing chart for explaining the operation of thefailure repair analyzing and processing apparatus shown in FIG. 2;

[0051]FIG. 4 is a block diagram showing an outline of a prior artgeneral memory testing apparatus;

[0052]FIG. 5 is a block diagram showing a detailed construction of thefailure repair analyzing and processing apparatus used in the memorytesting apparatus shown in FIG. 4;

[0053]FIG. 6 is a block diagram showing a detailed construction of thefailure analysis memory used in the memory testing apparatus shown inFIG. 5; and

[0054]FIG. 7 is a perspective view for explaining a construction of themulti-bit memory having redundancy structure.

BEST MODE FOR CARRYING OUT THE INVENTION

[0055] Now, a preferred embodiment of the present invention will bedescribed in detail with reference to FIGS. 1 to 3. The presentinvention may, however, be embodied in many different forms and shouldnot be construed as limited to the embodiment set forth hereinafter;rather, the embodiment described later on is provided so that thisdisclosure will be thorough and complete, and will fully convey thescope of the invention to those skilled in the art.

[0056]FIG. 1 is a block diagram showing a rough construction of anembodiment of the memory testing apparatus according to the presentinvention that is provided with a failure repair analyzing andprocessing apparatus using a method of analyzing and processing a repairof failure in a memory according to the present invention, and FIG. 2 isa block diagram showing a detailed construction of the failure repairanalyzing and processing apparatus shown in FIG. 1. In this memorytesting apparatus, a failure analysis memory 118 may be one that has thesame construction as that of the prior art failure analysis memory 118already discussed with reference to FIG. 6, and so the detailedconstruction thereof is not shown. Further, in FIGS. 1 and 2, elementsand portions corresponding to those shown in FIG. 5 will be denoted bythe same reference characters attached thereto, and explanation thereofwill be omitted unless necessary.

[0057] This embodiment is characterized in that a failure repairanalyzing and processing apparatus 119 is constituted by a control part10, two (first and second) repair analysis units 20A and 20B, an accesscontroller 30, a data distributor 40, and a unit select signal generator50, and in that an unprocessed data bit detector 11 and a data bitupdate device 12 are further provided in the control part 10.

[0058] The construction of each of the first and second repair analysisunits 20A and 20B may be one that has the same construction as that ofthe prior art repair analysis unit 20 shown in FIG. 5. Therefore, inthis embodiment, too, as shown in FIG. 2, each of the first and secondrepair analysis units 20A and 20B comprises: a bit specifying part 21constituted by a bit specifying register 21A, a group of AND gates 21Band an OR gate 21C for performing a logical addition (OR) of the ANDgate group 21B; a latch circuit 22 for temporarily storing dataoutputted from the bit specifying part 21; an operation and processingpart 23 for performing an operation or computation of data read out fromthe latch circuit 22; a failure block memory 25 for storing a memorycell array from which a failure memory cell is detected; and an addressgenerator 24 for generating an address signal for accessing an addressof the failure analysis memory 118 in carrying out a repair analysis andprocessing.

[0059] The first and second repair analysis units 20A and 20B starttheir repair analyzing operations when they receive analysis startsignals ALSRT1 and ALSRT2 respectively from the control part 10, andcause their address generators 24 to start to generate address signalsFADR1 and FADR2, respectively. The address signals FADR1 and FADR2generated respectively from their address generators 24 are applied tothe failure analysis memory 118 through the access controller 30. Theaccess controller 30 switches alternately the address signals FADR1 andFADR2 outputted respectively from the first and second repair analysisunits 20A and 20B to apply one address signal to the failure analysismemory 118. As a result, the two repair analysis units 20A and 20Balternately access the failure analysis memory 118 to read out from itsstorage part AFM failure data FAIL corresponding to failure memory cellinformation. The access controller 30 may be constituted of, forexample, a multiplexer.

[0060] The failure data FAIL read out from the failure analysis memory118 are sent to the data distributor 40 of the failure repair analyzingand processing apparatus 119 through a transmission line 60. The datadistributor 40 comprises: two (first and second) latch circuits 41 and42, and an inverter 43; and the failure data FAIL are applied torespective data input terminals D of these latch circuits 41 and 42. Theother input terminals G of the latch circuits 41 and 42 are invertinginput terminals, respectively. The inverting input terminal G of thefirst latch circuit 41 is connected directly to an output terminal ofthe unit select signal generator 50, and the inverting input terminal Gof the second latch circuit 42 is connected to the output terminal ofthe unit select signal generator 50 through the inverter 43.

[0061] The unit select signal generator 50 comprises: an OR gate towhich a first clock signal CK1 and a second clock signal CK2 areapplied; and a latch circuit having its clock terminal CK to which anoutput signal from the OR gate is applied. The unit select signalgenerator 50 generates a unit select signal UNSEL for selecting thefirst repair analysis unit 20A or the second repair analysis unit 20B.This unit select signal UNSEL outputted from the unit select signalgenerator 50 is supplied to the inverting input terminals G of the firstand second latch circuits 41 and 42 of the data distributor 40 asmentioned above as well as supplied to a control terminal of the accesscontroller 30 as shown in FIG. 1.

[0062] The data distributor 40 is configured such that it alternatelysupplies the failure data FAIL inputted from the failure analysis memory118 to the first and second repair analysis unit 20A and 20B under thecontrol of the unit select signal UNSEL. Specifically explaining, incase the first repair analysis unit 20A gives an address signal FADR1 tothe failure analysis memory 118 to access it, the data distributor 40 isarranged to input the failure data read out from that address of thefailure analysis memory 118 to the first repair analysis unit 20A. Incase the second repair analysis unit 20B gives an address signal FADR2to the failure analysis memory 118 to access it, the data distributor 40is arranged to input the failure data read out from that address of thefailure analysis memory 118 to the second repair analysis unit 20B.

[0063] When the repair analyzing operation for one data bit (one memorycell array group) has been completed, the first and second repairanalysis units 20A and 20B send respective analysis end signals ALEND1and ALEND2 to the control part 10.

[0064] Next, the operation of the failure repair analyzing andprocessing apparatus 119 constructed as discussed above will be furtherexplained with reference to a timing chart shown in FIG. 3.

[0065] The first and second clock signals CK1 and CK2 inputted to theunit select signal generator 50 are generated with the same period oftime duration 2T, as shown respectively in FIGS. 3A and 3C, and have aphase difference of time duration T between them. Accordingly, the firstand second clock signals CK1 and CK2 are alternately inputted to theunit select signal generator 50 with a period T.

[0066] The unit select signal generator 50 generates a unit selectsignal UNSEL shown in FIG. 3E, that inverts from logical “1” to logical“0” at each timing of the leading (rise) edge of the first clock CK1 aswell as inverts from logical “0” to logical “1” at each timing of theleading edge of the second clock CK2. This unit select signal UNSELbecomes a rectangular or square wave in which logical “0” and logical“1” are alternated for each time duration T, as shown in FIG. 3E, inthis embodiment since the first and second clock signals CK1 and CK2 aregenerated with the period 2T and with the phase difference T betweenthem.

[0067] In the first repair analysis unit 20A, the operation andprocessing part 23 reads out the stored data in the failure block memory25 therefrom, and if any failure memory cell does not exist in a memorycell array of a data bit (memory cell array group) for which the firstrepair analysis unit 20A intends to execute the repair analysis andprocessing, the operation and processing part 23 controls such that theaddress generator 24 does not generate an address signal to access thatmemory cell array and generates an address signal to access a subsequentmemory cell array to be analyzed and processed next time. That is, therepair analysis and processing for each of memory cell arrays from whichno failure memory cell has been detected is not carried out and therepair analysis and processing for a subsequent memory cell array to beanalyzed and processed next time is executed at once. The addressgenerator 24 generates an address signal FADR1 (addresses a, a+1, a+2,a+3, . . . , as shown in FIG. 3B, in synchronism with the leading edgeof the first clock signal CK1.

[0068] Likewise, in the second repair analysis unit 20B, the operationand processing part 23 reads out the stored data in the failure blockmemory 25 therefrom, and if any failure memory cell does not exist in amemory cell array of a data bit (a data bit different from the data bitfor which the first repair analysis unit 20A intends to execute therepair analysis and processing) for which the second repair analysisunit 20B intends to execute the repair analysis and processing, theoperation and processing part 23 controls such that the addressgenerator 24 does not generate an address signal to access that memorycell array and generates an address signal to access a subsequent memorycell array to be analyzed and processed next time. The address generator24 of the second repair analysis unit 20B generates an address signalFADR2 (addresses b, b+1, b+2, b+3, . . . ), as shown in FIG. 3D, insynchronism with the leading edge of the second clock signal CK2.

[0069] The access controller 30 alternately switches the address signalFADR1 and the address signal FADR2 in synchronism with the unit selectsignal UNSEL at intervals of the period T as shown in FIG. 3F, andoutputs the address signals alternately. As a result, an address signalFADR in sequence of addresses a, b, a+1, b+1, a+2, b+2, a+3, b+3, . . .is outputted from the access controller 30 and is applied to the failureanalysis memory 118. Since the switching rate of the address signalsFADR1 and FADR2 is equal to ½ of the period 2T of each of the firstclock signal CK1 and the second clock signal CK2, the address signalFADR consisting of the address signals FADR1 and FADR2 that are switchedat a rate twice the generation rate of the clock signal is applied tothe failure analysis memory 118.

[0070] The failure analysis memory 118 is accessed by the address signalFADR in which the addresses are switched at a rate twice the generationrate of the clock signal, and accordingly, the failure data FAIL inwhich failure data FD(a), FD(a+1), FD(a+2), . . . and failure dataFD(b), FD(b+1), FD(b+2), . . . existing in two respective data bitsalternate with each other with the period T is read out from the storagepart AFM of the memory 118 in sequence of FD(a), FD(b), FD(a+1),FD(b+1), FD(a+2), FD(b+2), . . . , as shown in FIG. 3G. That is, sincethe read-out period also becomes T, the failure data FAIL in which thefailure data existing in two respective data bits are switched at a ratetwice the generation rate of the clock signal is read out. The failuredata in which the respective failure data are switched at a rate twicethat of the clock signal is inputted to the data distributor 40 throughthe transmission line 60.

[0071] In the data distributor 40, the first and second latch circuits41 and 42 alternately take the failure data FAIL therein under thecontrol of the unit select signal UNSEL shown in FIG. 3E. These latchcircuits 41 and 42 hold the failure data taken therein, respectively,until the next first and second clock signals CLK1 and CLK2 are appliedto the latch circuits 41 and 42 respectively, and hence the failure dataFAIL1 latched in the first latch circuit 41 is switched at intervals ofthe period 2T as shown in FIG. 3H, and likewise, the failure data FAIL2latched in the second latch circuit 42 is also switched at intervals ofthe period 2T as shown in FIG. 31.

[0072] The failure data FAIL1 and FAIL2 latched respectively in thefirst and second latch circuits 41 and 42 are supplied to the otherinput terminals of the AND gate groups 21B of the respective bitspecifying parts 21 of the first and second repair analysis units 20Aand 20B, respectively. As a result, respective failure data in the databits (memory cell array groups) specified respectively by the bitspecifying registers 21A, 21A of the two repair analysis units 20A, 20Bare given to the latch circuits 22, 22 through the respective OR gates21C, 21C, and are latched therein. FIG. 31J shows the failure data FF1latched in the latch circuit 22 of the first repair analysis unit 20A,and FIG. 3K shows the failure data FF2 latched in the latch circuit 22of the second repair analysis unit 20B.

[0073] Each of the operation and processing parts 23, 23 of the firstand second repair analysis units 20A and 20B adds up in number thefailure data taken therein in each address line for each memory cellarray 202, and operates or computes and processes as to whether anaddress line on which one or more failure memory cells exist can berepaired by use of spare lines SC, SR provided on each memory cell array202. Moreover, each operation and processing part 23 reads out thestored data in the failure block memory 25 therefrom, and in case of amemory cell array from which any failure memory cell has not beendetected, the repair analysis and processing for that memory cell arrayfrom which no failure memory cell has been detected is not performed andthe repair analysis and processing for a subsequent memory cell array tobe analyzed and processed next time is carried out at once.

[0074] In this manner, this embodiment is constructed such that thefailure analysis memory 118 is accessed at a rate twice the generationrate of the address signals FADR1 and FADR2 generated from therespective address generators 24, 24 of the first and second repairanalysis units 20A and 20B, and the respective failure data FAIL1 andFAIL2 of two data bits are read out in sequence from the addresses ofthe failure analysis memory 118 to be taken in the first and secondrepair analysis units 20A and 20B in which the analysis and processingas to whether each memory cell array of the plural data bits (memorycell array groups) 201-0, 201-1, 201-2, . . . of the memory under test200 can be repaired by use of the spare lines SC, SR is carried out. Inother words, the embodiment is constructed that the first and secondrepair analysis units 20A and 20B execute the respective failure repairanalyses and processings one data bit by one data bit (one memory cellarray group by one memory cell array group) in parallel with each otherat the same time.

[0075] Here, a transmission line 61 for transmitting the address signalFADR from the access controller 30 to the failure analysis memory 118and the transmission line 60 for transmitting the failure data FAIL fromhe failure analysis memory 118 to the failure repair analysis andprocessing apparatus 119 are multi-bit transmission lines of, forexample, 16 bits or 32 bits or so, respectively. Accordingly, it isdifficult to provide these transmission lines independently orseparately in the first and second repair analysis units 20A and 20B.For this reason, in this embodiment, each of the transmission lines 60and 61 is used by time division or sharing so that the two repairanalysis units 20A and 20B can utilize them together.

[0076] Though the transmission lines 60 and 61 are utilized by timedivision, both the repair analysis units 20A and 20B are provided withtheir own address generators 24, 24, and hence, when the repair analysisunits 20A and 20B receive the analysis start signals ALSRT1 and ALSRT2respectively from the control part 10, they can start the respectivefailure repair analyses and processings independently.

[0077] The first and second repair analysis units 20A and 20B transmit,when they have completed the respective failure repair analyses andprocessings for the specified data bits, the analysis end signals ALEND1and ALEND2 respectively to the control part 10. The control part 10starts, when it receives the analysis end signals ALEND1 and ALEND2, anunprocessed data bit detector 11 to search as to whether an unprocesseddata bit exists or not. When an unprocessed data bit has been detected,the control part 10 gives information of that unprocessed data bit tothe data bit update device 12. The data bit update device 12 updates abit specifying signal BITSP that is given to the bit specifying register21A of the repair analysis unit 20A or 20B from which the analysis endsignal ALEND1 or ALEND2 has been transmitted to the detected unprocesseddata bit.

[0078] Accordingly, in the state that one repair analysis unit, forexample, the first repair analysis unit 20A does not end the failureanalysis and processing for a memory cell array group corresponding to adata bit that was assigned to the first repair analysis unit 20A, forexample, the failure analysis and processing for the bit 1 memory cellarray group 201-0, if the second repair analysis unit 20B has completedthe failure analysis and processing for a memory cell array groupcorresponding to a data bit that was assigned to the second repairanalysis unit 20B, for example, the failure analysis and processing forthe bit 2 memory cell array group 201-1, then the control part 10specifies the third data bit bit-2 to the second repair analysis unit20B thereby to cause the second repair analysis unit 20B to execute thefailure analysis and processing for the bit 3 memory cell array group201-2. Thereafter, when the first repair analysis unit 20A has completedthe failure analysis and processing for the bit 1 memory cell arraygroup 201-0, the control part 10 specifies the fourth data bit bit-3 tothe first repair analysis unit 20A thereby to cause the first repairanalysis unit 20A to perform the failure analysis and processing for thebit 4 memory cell array group 201-3.

[0079] In such manner, according to the embodiment discussed above, boththe repair analysis units 20A and 20B can receive respective assignmentsof data bits independently thereby to carry out their repair analysisand processing operations without being affected by the delay of therepair analysis and processing operation of one repair analysis unit.Accordingly, even if the processing speed of one repair analysis unitthat executes the failure repair analysis and processing for a memorycell array in which many failure memory cells exist is lowered, theother repair analysis unit runs on its failure repair analysis andprocessing operation. Consequently, the failure repair analysis andprocessing time of the whole of the apparatus is reduced and the failurerepair analysis and processing can be carried out at high speed.

[0080] In other words, the two repair analysis units are concurrentlyoperated in parallel with each other, and in case one repair analysisunit has completed the failure repair analysis and processing for a databit (memory cell array group) prior to a data bit for which the otherrepair analysis unit is performing the failure repair analysis andprocessing, the one repair analysis unit can receive assignment of adata bit that the failure repair analysis and processing therefor is tobe executed next time, and thereafter, it can execute the repairanalysis and processing for that data bit. Accordingly, even if thereoccurs a delay in the processing time of one repair analysis unit thatperforms the repair analysis and processing for a data bit in which manyfailure memory cells exist, the other repair analysis unit can carry outthe failure repair analysis and processing for the next data bit priorto the one repair analysis unit. As a result, even if a number offailure memory cells exist biasedly in a specified memory cell array,the influence thereof is reduced, and the failure repair analysis andprocessing can be completed in a short time as a whole.

[0081] In the aforementioned embodiment, for clarity of explanation, thetwo repair analysis units 20A and 20B are provided in the failure repairanalysis and processing apparatus 119. However, it is needless to saythat three or more repair analysis units having the same constructionwith one another may be provided in the failure repair analysis andprocessing apparatus 119. If the number of repair analysis units isfurther increased, the failure repair analysis and processing may becarried out at higher speed. For example, if the number of failurerepair analysis units is N, the failure repair analysis time can bereduced to 1/N.

[0082] In addition, though there is described the case that the analysisand processing is carried out as to whether a failure memory cell orcells detected from each of the data bits of the multi-bit memory ofredundancy structure can be repaired or not, the present invention maybe applied to a case that the analysis and processing is carried out asto whether a failure memory cell or cells detected from a memory ofredundancy structure other than multi-bit memories (that is, one bitmemory of redundancy structure) can be repaired or not, and the failurerepair analysis and processing may be carried out at high speed as inthe above embodiment.

[0083] In case a memory under test is not a multi-bit memory, respectivefailure data representing failure memory cells of plural memory cellarrays of the memory under test are stored in plural data bit memoryareas of the failure analysis memory, respectively, the plural data bitmemory areas of the failure analysis memory being ones in which, in casethat the memory under test is a multi-bit memory, respective failuredata each representing failure memory cells for each data bit arestored. In other words, failure data representing a failure memory cellor cells of one memory cell array of the memory under test are storedonly in corresponding one data bit memory area of the failure analysismemory 118. Accordingly, in case the memory under test is not amulti-bit memory, respective failure data read out from the plural databit memory areas of the failure analysis memory 118 are ones that havebeen detected respectively from the plural memory cell arrays of thetested memory.

[0084] As is clear from the foregoing, according to the presentinvention, a plurality of repair analysis units as well as a commonfailure analysis memory are provided, and these repair analysis unitsare concurrently operated in parallel with each other to carry out theirrepair analyses and processings for a plurality of data bits or aplurality of memory cell arrays. Accordingly, there are obtainedremarkable advantages that the repair analysis and processing time canbe greatly reduced and hence the failure repair analysis and processingcan be executed at high speed. Thus, there can be provided a method ofanalyzing and processing a repair of failure in a memory and a memorytesting apparatus using this method, that are capable of coping with theincreasing storage capacity of and the increasing number of bits of amemory.

[0085] While the present invention has been described with regard to thepreferred embodiment shown by way of example, it will be apparent tothose skilled in the art that various modifications, alterations,changes, and/or minor improvements of the embodiment described above canbe made without departing from the spirit and the scope of the presentinvention. Accordingly, it should be understood that the presentinvention is not limited to the illustrated embodiment, and is intendedto encompass all such modifications, alterations, changes, and/or minorimprovements falling within the scope of the invention defined by theappended claims.

What is claimed is:
 1. A method of analyzing and processing a repair offailure that is carried out in a memory testing apparatus whichcomprises: a failure analysis memory for storing therein failure datarepresenting a failure memory cell or cells of a memory under testhaving redundancy structure; and a failure repair analyzing andprocessing apparatus for analyzing as to whether the failure memory cellor cells of the memory under test can be repaired on the basis of thefailure data read out from the failure analysis memory after the testinghas been completed, said method comprising the steps of: reading outfailure data respectively from plural specified data bit memory areas ofthe failure analysis memory in sequence and distributing them tocorresponding plural repair analysis units respectively; and operatingconcurrently the plural repair analysis units in parallel with eachother and causing the units to carry out concurrently their repairanalyses and processings for the failure memory cell or cellscorresponding to the failure data read out from the failure analysismemory in parallel with each other.
 2. The method of analyzing andprocessing a repair of failure as set forth in claim 1, furtherincluding: the step of checking whether there exists an unprocessed databit memory area for which the repair analysis and processing is notexecuted or not, and wherein in case an unprocessed data bit memory areahas been detected, each of the repair analysis units performs, when ithas completed the repair analysis and processing for failure data of adata bit memory area assigned to that unit, the repair analysis andprocessing for failure data of the detected unprocessed data bit memoryarea at once.
 3. The method of analyzing and processing a repair offailure as set forth in claim 1 or 2, wherein said step of reading outfailure data respectively from plural specified data bit memory areas ofthe failure analysis memory in sequence includes the step of: switchingin sequence respective address signals accessing to plural specifieddata bit memory areas, that are outputted respectively from the pluralrepair analysis units to apply them to the failure analysis memory; andwherein the period that the plural address signals are switched insequence is a period that the period of each address signal accessing tocorresponding one specified data bit memory area is divided by thenumber of specified data bit memory areas; and wherein the failure dataread out from the failure analysis memory are failure data that areswitched in sequence at intervals of the same period as the switchingperiod of the address signals applied to the failure analysis memory. 4.A memory testing apparatus comprising: a failure analysis memory forstoring therein failure data representing a failure memory cell or cellsof a memory under test having redundancy structure; a plurality ofrepair analysis units, each being constructed such that it specifies anydata bit memory area in plural data bit memory areas of the failureanalysis memory, reads out failure data stored in the specified data bitmemory area in respective failure data stored in the plural data bitmemory areas of the failure analysis memory, and analyzes as to whethera memory cell array or arrays associated with the read-out failure datacan be repaired or not; access control means for switching in sequencerespective address signals outputted from the plural repair analysisunits to apply them to the failure analysis memory in sequence; datadistributing means for distributing respective failure data read outfrom the plural specified data bit memory areas of the failure analysismemory to the corresponding plural repair analysis units, respectively;and a control part that controls respective repair analysis andprocessing operations of the plural repair analysis units.
 5. The memorytesting apparatus as set forth in claim 4, wherein each of the pluralrepair analysis units is provided with its own address generator, andeach repair analysis unit can access the failure analysis memoryseparately and independently of the operation of other repair analysisunit or units by generating an address signal accessing to a specifieddata bit memory area from its own address generator.
 6. The memorytesting apparatus as set forth in claim 4, wherein the access controlmeans is arranged such that it switches in sequence respective addresssignals accessing to plural specified data bit memory areas, that areoutputted respectively from the plural repair analysis units to applythem to the failure analysis memory; and wherein the period that theplural address signals are switched in sequence is a period that theperiod of each address signal accessing to corresponding one specifieddata bit memory area is divided by the number of specified data bitmemory areas; and wherein the failure data read out from the failureanalysis memory are failure data that are switched in sequence atintervals of the same period as the switching period of the addresssignals applied to the failure analysis memory.
 7. The memory testingapparatus as set forth in any one of claim 4, 5 or 6, wherein thecontrol part applies respective analysis start signals, respective bitspecified signals, and respective load signals to the plural repairanalysis units, respectively, and receives a analysis end signal fromeach of the plural repair analysis units, thereby to control respectiverepair analysis and processing operations of the plural repair analysisunits; and the control part further comprises: unprocessed data bitdetecting means for detecting, each time a repair analysis unit that hascompleted the repair analysis and processing operation for a memory cellarray or arrays associated with failure data of a specified data bitmemory area transmits an analysis end signal, whether there exists anunprocessed data bit memory area for which the repair analysis andprocessing is not executed or not; and data bit update means forupdating, in case an unprocessed data bit memory area has been detected,a bit specifying signal being applied to a repair analysis unit that hascompleted the repair analysis and processing operation to a bitspecifying signal to be applied to the unprocessed data bit memory area.8. The memory testing apparatus as set forth in any one of claim 4, 5 or6, wherein the memory under test is a multi-bit memory; and wherein thefailure analysis memory includes at least the same number of data bitmemory areas as the number of bits of the memory under test, and failuredata of each of the data bits of the multi-bit memory under test arestored in corresponding one data bit memory area of the failure analysismemory.
 9. The memory testing apparatus as set forth in any one of claim4, 5 or 6, wherein the memory under test is a one-bit memory; andwherein the failure analysis memory includes at least the same number ofdata bit memory areas as the number of memory cell arrays of the memoryunder test, and failure data of each of the memory cell arrays of thememory under test are stored in corresponding one data bit memory areaof the failure analysis memory.